What happens next
- Applications closed — 09 Sep 2026
IIEST Project Associate VLSI Recruitment 2026
Indian Institute of Engineering Science and Technology, Shibpur (IIEST Shibpur) - School of VLSI Technology
Published Source: Official Notification Report an error
Vacancy
1
Salary
₹30,000 - ₹30,000
Job Type
Contract
Full time
Apply By
09 Sep 2026
This recruitment closed on 09 Sep 2026
Applications are no longer being accepted for IIEST Project Associate VLSI Recruitment 2026. Applications are closed. Browse related open jobs below.
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About This Job
Apply for 1 Project Associate VLSI post at IIEST Shibpur. M.Tech with experience eligible. Salary: Rs 30,000. Walk-in: 9 Sep 2026.
IIEST Project Associate VLSI Recruitment 2026: Overview
Indian Institute of Engineering Science and Technology, Shibpur (IIEST Shibpur) is selecting a Project Associate-I for the School of VLSI Technology. The role belongs to a sponsored research project on a system-on-chip platform for next-generation Internet of Things use in Industry 4.0, with functional safety and security built into the design. The project is supported through the Chip to Startup programme of the Ministry of Electronics and Information Technology, making this a hands-on semiconductor research opportunity rather than a general campus administration post.
Your background should connect directly with analog and mixed-signal design. The desirable areas named in the notice include FPGA work, coding, chip tape-out and integrated-circuit testing, so the panel can look beyond the degree certificate and ask what you have actually designed, simulated, programmed or tested. A concise portfolio of project work, publications, tape-out exposure or laboratory results can help you explain that experience clearly at the walk-in.
Service Conditions and Caveats
- Project-linked tenure: The engagement is planned for two years or until the sponsored project finishes, whichever condition governs the project. It does not create a claim to a permanent institute post.
- Yearly review: Continuation is subject to an annual evaluation of your contribution to project execution, so progress, documentation and dependable laboratory work will matter after selection.
- Technical focus: The work sits within the School of VLSI Technology and centres on an SoC-based IoT system for industrial use, including functional-safety and security concerns.
- Document accuracy: The institute will verify records at joining and can cancel the selection if it finds a discrepancy. Make sure the experience claimed in your bio-data matches your certificates.
- Communication: Your application letter and bio-data must carry a valid email address and phone number so the project team can contact you after the interview.
- Travel costs: The institute will not pay TA or DA for attending the walk-in, so you need to arrange and fund your travel to Shibpur.
Application Submission Notes
This is a walk-in interview at the School of VLSI Technology, IIEST Shibpur, Howrah 711103. Prepare an application letter on plain paper and take a recent bio-data. There is no online form or email submission route stated in the notice, so your physical attendance and complete papers are essential.
Bring self-attested photocopies of mark sheets, certificates, work-experience proof and a valid identity document. Arrange them in the same order as your bio-data and keep originals available in case the institute wants to cross-check details. The notification says formal verification will happen at joining, and any mismatch can cancel the selection.
Before attending, review how your past work connects with analog circuits, mixed-signal design, FPGA development, coding, tape-out and IC testing. The project title combines hardware design with industrial IoT, safety and security, so be ready to explain both your core contribution and how you worked with a wider system or research team.
Responsibilities
- Design and evaluate analog and mixed-signal circuit blocks for the project
- Develop FPGA or embedded prototypes for the SoC-based IoT system
- Write and test code needed for hardware integration and experiments
- Support chip tape-out preparation, validation and IC testing activities
- Record design choices, test results and project progress clearly
- Coordinate research tasks with the principal investigator and project team
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Join our TelegramEligibility Criteria
Minimum Qualification
M.Tech with 7.0 CGPA and one year of experience in Analog and Mixed Signal Design, subject to institute norms.
Preferred Qualification
Experience in Analog and Mixed Signal Design, FPGA, coding, chip tape-out and IC testing.
Required Skills
Analog and mixed-signal design, FPGA development, coding, chip tape-out and IC testing.
Age Limit
18 - 35 years
Age Relaxation:
- SC/ST/OBC/Women/PwD: 5 years
Experience
1 - No limit years
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Salary & Compensation
Pay Scale
INR 30,000 per month (consolidated)
Selection Process
- 1 Interview
- 2 Document Verification
How to Apply
Application Mode: Offline
Required Documents:
- Application letter on plain paper
- Recent bio-data with valid email address and phone number
- Self-attested photocopies of mark sheets
- Self-attested photocopies of educational certificates
- Self-attested work-experience certificate
- Valid identity proof
Frequently Asked Questions
The walk-in interview is on 9 September 2026 at 11:00 AM at the School of VLSI Technology, IIEST Shibpur.
You need an M.Tech with 7.0 CGPA and one year of experience in Analog and Mixed Signal Design, subject to institute norms.
Attend the walk-in at the School of VLSI Technology, IIEST Shibpur with a plain-paper application, bio-data and the prescribed self-attested documents.
The selected Project Associate-I will receive INR 30,000 per month as consolidated pay.
Selection is through a walk-in interview, followed by document verification at joining.
Important Dates
Notification
27 Aug 2026
Application Start
27 Aug 2026
Last Date to Apply
09 Sep 2026
Job Locations
Categories
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