NIT Trichy JRF (ECE) Recruitment 2026

NIT Tiruchirappalli (NIT Trichy) is hiring 1 Junior Research Fellow (JRF) for a research project in the Department of Electronics and Communication Engineering (ECE). If you have a B.E./B.Tech or M.E./M.Tech (First Class) in ECE, EEE, or Instrumentation and Control Engineering with a valid GATE score, you can apply by email. The last date to apply is 23 July 2026, 5:00 PM. The age limit is 28 years, and the salary is Rs. 37,000 per month plus 20% HRA.

National Institute of Technology, Tiruchirappalli (NIT Trichy) JRF (ECE) Recruitment 2026 - 1 Post

NIT Trichy has released a notification for 1 Junior Research Fellow position under an Anusandhan National Research Foundation (ANRF) project funded through the Prime Minister Early Career Research Grant (PMECRG) scheme. The project is led by Dr. Manikandan R R, Assistant Professor in the Department of Electronics and Communication Engineering, and is titled "Zero Temperature Coefficient (ZTC) Operating Point Based PMU Infrastructure Circuits."

The work covers miniaturized DC-DC buck converters and nano-power MOSFETs, and involves designing power management integrated circuits, running analog circuit simulations in CADENCE, layout design and parasitic extraction, full-chip IP integration, chip tape-out, and PCB design for testing. Selected candidates also get the opportunity to register for a PhD or M.S. (By Research) program at NIT Trichy, subject to fulfilling institute norms — a good fit if you want to build a research career in VLSI and power electronics.

Who Can Apply?

• Qualification: B.E./B.Tech or M.E./M.Tech (First Class) in Electronics and Communication Engineering, Electrical and Electronics Engineering, or Instrumentation and Control Engineering from a UGC recognized university
• Mandatory: Valid GATE score in a subject related to the discipline you are applying under
• Selection basis: Your GATE score, percentage of marks in your qualifying degree, relevant experience, and other criteria set by the selection committee

Only candidates who have been awarded their Degree or Provisional Certificate can apply.

Age Limit

• You should be below 28 years old as on the closing date of the advertisement.
• Age Relaxation: SC/ST candidates get 5 years relaxation, and OBC candidates get 3 years relaxation.

Salary

• Selected candidates will get Rs. 37,000 per month plus 20% HRA.
• The project appointment is initially for 3 months, extendable up to a maximum of 3 years.

Selection Process (No Written Exam)

There is no written exam for this post. Selection is based on:

1. Shortlisting: Based on your GATE score, percentage of marks in your qualifying degree, and relevant experience.
2. Interview: Shortlisted candidates are called for an interview at NIT Trichy. A minimum 14 days' notice is given for a regular interview, and a minimum 5 days' notice for a walk-in interview.
3. Document Verification: Bring original certificates (educational qualifications, category, age proof, GATE score, and NOC if applicable) for verification at the interview.

No TA/DA is paid for attending the interview, and you must arrange your own stay and travel to NIT Trichy. For JRF, your GATE paper and qualifying degree subject must be related to the discipline you are applying under.

How to Apply

1. Download the prescribed application format (Form No. 8) from the nitt.edu job opportunities page.
2. Fill in your details and attach self-attested copies of your degree certificates, mark sheets, and GATE scorecard.
3. Scan your completed application and supporting documents as a single PDF.
4. Email your application to manirr8687.nitt@gmail.com before the last date.
5. For queries, contact Dr. Manikandan R R at 9535144501 between 2:30 PM and 5:00 PM on working days.

If you are already employed with the government or a PSU, bring a No Objection Certificate (NOC) from your employer to the interview — otherwise you will not be allowed to appear.

Important Dates

• Notification Date: 7 July 2026
• Last Date to Apply: 23 July 2026, 5:00 PM

• Design power management integrated circuits for the project
• Perform analog circuit simulation using CADENCE tools
• Handle layout design and parasitic extraction
• Support full chip IP integration and chip tape-out activities
• Design PCBs for chip testing and conduct experiments
• Characterize power management circuits and analyze results
• Prepare technical reports and research articles