TIFR Project Engineer CMS Recruitment 2026

TIFR Project Engineer CMS Recruitment 2026

Tata Institute of Fundamental Research (TIFR) - Department of High Energy Physics, TIFR Mumbai

Published Source: Official Notification Report an error

Vacancy

1

Salary

₹60,000 - ₹60,000

Job Type

Temporary

Full time

Apply By

30 Sep 2026

About This Job

Apply for the TIFR Project Engineer vacancy. B.E./B.Tech with 60% and 1 year of circuit-design experience needed. Salary: Rs 60,000. Last date: 30 Sep 2026.

TIFR Project Engineer CMS Recruitment 2026: Overview

Tata Institute of Fundamental Research (TIFR), an autonomous institution under the Department of Atomic Energy, is hiring a Project Engineer for its Department of High Energy Physics in Mumbai. The role supports India's participation in the CMS experiment at CERN, with work centred on the electronics that collect and move data from particle detectors. This is a hands-on engineering assignment where your circuit designs, firmware and test work will connect directly with a major international physics collaboration.

The post sits between experimental physics and advanced electronics. You will work with physicists and engineers on detector readout systems rather than a general campus-maintenance project. The strongest fit is someone comfortable moving from simulation and PCB design to laboratory debugging and live detector support.

Service Conditions and Caveats

  • Project tenure: The appointment is temporary for an initial period of one year. It may be extended for up to another two years when performance and project needs support an extension.
  • Employment status: The appointment is non-pensionable and does not create a claim to another temporary or permanent post at TIFR during or after the project.
  • Operational support: The CMS detector work can include on-call hardware support, so you should be ready to diagnose faults and coordinate with the wider technical team when systems are in operation.
  • Engineering environment: The work spans mixed-signal electronics, detector data acquisition, embedded processors and high-speed links. You may need to shift between design tools, bench testing and collaboration meetings as the project moves through maintenance and upgrade tasks.

Application Submission Notes

Send your application by email to rajdeep.chatterjee@tifr.res.in and shilpi.jain@tifr.res.in. Use the subject "Application for Project Engineer (Name of the candidate)" so the project team can identify your application correctly.

Your CV must follow the format specified in Advertisement No. 2026/26. It should cover personal details, academic history in the requested table, the qualifying degree record and contact details for two referees. Add a brief statement that connects your practical electronics experience to the detector-readout work described in the notice.

Keep the CV focused: the notice asks applicants not to add extra information or pages outside the prescribed format. Attach copies of relevant certificates and make sure the experience statement clearly explains your work with analog, digital or VLSI circuits, firmware, PCB bring-up or comparable high-speed systems.

Responsibilities

  • Design, simulate and debug low-noise analog front-end circuits for particle-detector readout
  • Develop and validate high-speed digital and VLSI systems using CPLDs and FPGAs
  • Write and maintain Verilog or VHDL firmware for FPGA-based readout systems
  • Implement and test high-speed data links used for detector data acquisition
  • Program soft processors embedded in FPGA-based systems
  • Collaborate with physicists and engineers on PCB design, layout and board bring-up
  • Support CMS detector operations and handle on-call hardware maintenance

Eligibility Criteria

Minimum Qualification

B.E./B.Tech in Electronics Engineering or Electronics and (Tele)Communications Engineering with at least 60% aggregate marks

Preferred Qualification

Familiarity with particle-detector data acquisition, end-to-end PCB electronics design, and Verilog or the Vivado design suite

Required Skills

Low-noise analog circuit design; ADCs and power management; FPGA/CPLD synthesis, timing closure and simulation; Verilog/VHDL; Vivado or Quartus; LVDS, GbE, PCIe or similar serial links; Altium or KiCad; mixed-signal board bring-up

Age Limit

18 - 29 years (as on 30 Sep 2026)

Experience

1.0 - No limit years

Am I eligible?

Quick self-check against this job's age & qualification. Indicative only — always confirm with the official notification.

✓ You look eligible ⚠ Borderline — check age relaxation ✗ You may not be eligible

  • You're below the minimum age ().
  • You're above the maximum age ().
  • Above the general age limit (), but you may qualify under reserved-category relaxation (up to ).
  • This post needs a higher qualification than the one selected.
  • Couldn't auto-check the qualification — see the criteria above.

Get Research jobs in Maharashtra

One tap. Get notified the moment a matching notification is posted.

✓ You'll get these alerts.

Salary & Compensation

Pay Scale

Comprehensive monthly salary of Rs. 60,000

Selection Process

  1. 1 Interview

Additional Requirements

Computer Knowledge Required

How to Apply

Application Mode: Offline

Click the "Apply Now" button to visit the official application portal.

Required Documents:

  • Detailed CV in the format prescribed in Advertisement No. 2026/26
  • Final marksheet and/or degree certificate for the eligible degree
  • Copies of relevant certificates
  • Brief statement of relevant experience
  • Academic history in the prescribed table format
  • Names, email addresses and contact numbers of two referees

Frequently Asked Questions

The last date for TIFR to receive your email application is 30 September 2026. Send the complete CV and attachments before the deadline.

The post carries a comprehensive monthly salary of Rs. 60,000.

You need a relevant B.E./B.Tech with at least 60% marks and a minimum of one year of hands-on high-speed circuit-design and debugging experience.

Email the prescribed CV, certificates and experience statement to the two project contacts named in the notice. Use "Application for Project Engineer (Name of the candidate)" as the subject.

TIFR will select the Project Engineer through a personal interview.

Similar Jobs

Central Government Teaching
05 Oct 1 posts

IIT Jammu Research Associate NTTM Recruitment 2026

Indian Institute of Technology Jammu (IIT Jammu)

Teaching Research
30 Sep 1 posts

NIT Goa Faculty Recruitment 2026

National Institute of Technology Goa (NIT Goa)

Central Government NIT
30 Sep 28 posts

CAU Comptroller Recruitment 2026

Central Agricultural University (CAU), Imphal

Teaching College/University
30 Sep 2 posts

VECC Principal Project Associate CSE 2026

Variable Energy Cyclotron Centre (VECC)

Research Teaching
30 Sep 1 posts

More from Tata Institute of Fundamental Research (TIFR)

View all Tata Institute of Fundamental Research (TIFR) jobs →

TIFR Multi-Post Recruitment 2026

Tata Institute of Fundamental Research (TIFR)

Research Teaching
15 Sep 5 posts

TIFR Project Staff Recruitment 2026

Tata Institute of Fundamental Research (TIFR)

Research Teaching
15 Sep 5 posts

TIFR Professor & Reader Recruitment 2026

Tata Institute of Fundamental Research (TIFR)

Teaching College/University
31 Dec 1 posts