IITH Analog IC Designer Recruitment 2026

IITH Analog IC Designer Recruitment 2026: Overview

Indian Institute of Technology Hyderabad (IITH) is hiring one Analog IC Designer on a full-time contract for an R&D project run out of its IC Design Lab. The work sits in analog and mixed-signal integrated circuit design — you will design circuits at the transistor level, simulate them, and see them through layout and silicon validation. This is a hands-on chip design role, not a teaching or pure research post, so it suits someone who has already spent a few years on industry-standard analog EDA tools.

Service Conditions and Caveats

• Contract term: The first contract runs for one year. Any extension depends on your performance and the project's needs.
• PhD wording: The notice lists the qualification under "Preferred Qualification" but also calls the PhD mandatory. Treat the PhD as a must-have when you decide whether to apply.
• Joining: The selected candidate is expected to join on 20 November 2026, so be ready to move quickly if you are shortlisted.
• Place of work: You will work on campus at the IC Design Lab, IIT Hyderabad.
• Toolchain: Day-to-day work uses Cadence Virtuoso, Spectre and ADE along with foundry PDKs and device models, so prior hands-on use of these tools will help your case.

Application Submission Notes

There is no online form for this post. Email your latest resume to prahaseeth.manne@ee.iith.ac.in. The notice treats the closing day as the last date to receive CVs, so send yours early rather than on the final evening.

• Design analog and mixed-signal integrated circuits at the transistor level
• Build schematics and testbenches, and run pre-layout simulations in Cadence Virtuoso, Spectre and ADE
• Design analog blocks such as op-amps, comparators, current mirrors, bias circuits, bandgap references and LDOs
• Run DC, AC, transient, noise, stability, PVT corner and Monte Carlo simulations to check circuit performance
• Tune circuits for power, performance, area, gain, bandwidth, noise and stability
• Work with layout engineers on floorplanning, matching and layout reviews, then run post-layout simulations with parasitic extraction
• Follow foundry PDKs, device models and design rules to keep designs compliant
• Support design reviews, documentation, silicon characterisation and validation with cross-functional teams