IITGN Project Associate I Electrical Recruitment 2026

IITGN Project Associate I Recruitment 2026: Overview

Indian Institute of Technology Gandhinagar (IITGN) is hiring a Project Associate-I in its Department of Electrical Engineering to work with Prof. Joycee Mekie. The appointment supports a Ministry of Electronics and Information Technology (MeitY) sponsored project under C2S, centred on a secure, energy-efficient mixed-domain compute-in-memory AI accelerator chip for edge applications.

The project combines digital and analogue circuit work with chip design, so its focus is more specific than the broad Project Associate title suggests. You would join this research project at IIT Gandhinagar through a fixed-term appointment, with Prof. Mekie named as the principal investigator and contact for the advertisement.

Service Conditions and Caveats

• Appointment period: The notice sets a one-year engagement for this project position. If you are considering the role, plan around that stated term rather than assuming a continuing institute appointment.
• Recruitment rules: The advertisement marks funding-agency norms as the basis for this appointment. The project-specific conditions in this notice therefore matter when you assess the opportunity.
• Shortlisting: Meeting the minimum conditions does not promise a call or an appointment. IITGN can use a higher cutoff when deciding which applications to take forward.
• Institute discretion: IITGN may decide against calling an applicant for a selection test. It also keeps the option to leave the position unfilled in this recruitment round, without giving a reason.
• Project contact: Prof. Joycee Mekie in the Electrical Engineering department is the named contact. The advertisement gives joycee@iitgn.ac.in for contact, while directing applications through its separate project-staff portal.

• Support the MeitY-sponsored C2S chip research project.
• Apply digital-circuit knowledge to the project work.
• Apply analogue-circuit knowledge to the project work.
• Contribute to VLSI design for the AI accelerator chip.
• Use relevant VLSI tools and techniques in the research.