IITR ECE Junior Research Fellow Recruitment 2026

IIT Roorkee is hiring 1 Junior Research Fellow in the Electronics and Communication Engineering Department. If you have B.E./B.Tech in ECE or equivalent with GATE qualification, you can apply through the process given in the notice. The last date to submit the application is 30 June 2026. Salary is Rs. 37,000 per month + HRA as per institute rules.

Indian Institute of Technology Roorkee Junior Research Fellow Recruitment 2026 - 1 Post

Indian Institute of Technology Roorkee (IIT Roorkee) has released a project staff notice for the Department of Electronics and Communication Engineering. The post is linked to the ANRF Delhi project titled A parasitic and mechanical stress aware design methodology for novel EDA compatible buffer-TSV standard cells for 3D ICs. There is no written exam mentioned; shortlisted candidates will be informed about the online interview by email.

This is a one-year project appointment, extendable up to the end of the project based on review after 6 months. The notice says the selected candidate may get an opportunity for PhD admission, and GATE is mentioned as mandatory.

Who Can Apply?

Educational Qualification

• Minimum qualification: You need B.E./B.Tech in Electronics and Communication Engineering or an equivalent degree.
• Preferred qualification: M.E./M.Tech in Microelectronics, VLSI or equivalent is preferred.
• GATE condition: You should be GATE qualified.
• Project fit: You should have knowledge of semiconductor device physics, network theory and VLSI circuit design.
• CMOS exposure: Exposure to CMOS logic design is mentioned in the notice.

Useful Technical Skills

• EDA and TCAD tools: Cadence tools suite, SPICE and Sentaurus TCAD device/process simulation.
• Hardware language: Verilog.
• Programming/tools: MATLAB and Python.
• Team fit: You should be ready to coordinate and work with collaborating industry partners.

Salary

• Monthly salary: Rs. 37,000.
• Allowance: HRA as per institute rules.
• Tenure: 1 year, extendable till the end of the project after periodic review.

Selection Process (No Written Exam)

The notice mentions an online interview for shortlisted candidates. No written paper, marks, exam duration or negative marking is given.

1. Application submission: Submit your application before 30 June 2026.
2. Eligibility screening: IIT Roorkee will check your ECE/VLSI qualification, GATE status and project fit.
3. Shortlist email: Shortlisted candidates will receive the online interview date by email.
4. Online interview: Attend the interview with the required documents ready for verification.
5. Final selection: Selection will depend on your technical fit and interview performance.

The notice says no TA/DA will be paid for attending the interview. Preference will be given to SC/ST candidates when qualifications and experience are equal.

How to Apply

1. Prepare your application for the post of JRF in the ANRF project.
2. Use the subject line Application for the post of JRF in ANR-3032-ECD-TSAW26-27 where email submission is used.
3. Keep your CV, degree certificates, GATE proof and experience proof ready.
4. Submit the application through the mode specified by the ECE department before 30 June 2026.
5. Check your email regularly for the online interview schedule.
6. Bring or keep original degree and experience certificates ready for verification.

Documents to Keep Ready

• Application for JRF with correct project subject line.
• B.E./B.Tech or M.E./M.Tech certificates and mark sheets.
• GATE qualification proof.
• CV showing ECE, VLSI, CMOS, EDA or TCAD work.
• Experience certificates, if you mention experience.
• Original certificates for verification during the selection process.

Important Dates

• Notification Date: 11 June 2026
• Application Start: 11 June 2026
• Last Date to Apply: 30 June 2026
• Online Interview Date: To be informed by email

• Support research on parasitic and mechanical stress aware EDA design methods for 3D ICs
• Work with buffer-TSV standard cell concepts and related VLSI design tasks
• Use EDA and TCAD tools such as Cadence, SPICE and Sentaurus for project work
• Prepare Verilog, MATLAB or Python based design and analysis support when needed
• Keep simulation results, design notes and project records properly organised
• Coordinate with the project investigator and collaborating industry teams
• Follow institute and lab procedures while working on semiconductor and VLSI tasks