IIT Jammu JRF VLSI Design Recruitment 2026

IIT Jammu JRF VLSI Design Recruitment 2026: Overview

Indian Institute of Technology Jammu (IIT Jammu) is hiring a Junior Research Fellow (JRF) for the project Towards Trusted-node Free Hybrid Quantum Secure Communication Network (TAHQEECAT). The Department of Science and Technology supports this work through the National Quantum Mission (NQM), with the Department of Electrical Engineering at IIT Jammu providing the contact for this opening.

The project brings together Very Large Scale Integration (VLSI) design, cryptography and digital signal processing for quantum key distribution systems. You would work on the hardware side of this research, whose stated scope runs from hardware-friendly algorithms and Field-Programmable Gate Array (FPGA) systems to Application-Specific Integrated Circuit (ASIC) design and chip tape-out.

Service Conditions and Caveats

• Initial tenure: The appointment begins with a six-month term. An extension depends on your performance, so the initial offer does not promise employment for the entire remaining life of the research project.
• Project-linked appointment: The fellowship ends with the project. You should consider the position as a research engagement tied to this funded work when planning your availability and any move to Jammu.
• Application accuracy: You are responsible for the information, photographs and supporting material you provide. Check that your application accurately represents your academic record and research background.
• Communication: Keep your email address and phone number accurate in the application. IIT Jammu uses email to contact shortlisted applicants, including to share interview arrangements.
• Interview arrangements: The institute may hold interviews online or offline. Follow the instructions sent to you before making travel plans, as the notice leaves both formats open.
• Travel costs: You must pay your own travel costs if asked to attend at IIT Jammu. The institute will not pay travel or daily allowances for an offline interview or for joining after an offer.
• Language of the notice: The advertisement presents information in English and Hindi. The English version takes precedence if the wording causes doubt.

• Develop hardware-friendly algorithms for quantum key distribution tasks.
• Design digital VLSI architectures for signal processing and post-processing.
• Implement and test FPGA-based system designs.
• Develop Verilog or VHDL designs for the project's hardware tasks.
• Use electronic design automation tools for ASIC design and verification.
• Support chip tape-out work and record design and test results.