NITT JRF ECE Recruitment 2026
National Institute of Technology Tiruchirappalli - Department of Electronics and Communication Engineering
प्रकाशित स्रोत: आधिकारिक अधिसूचना त्रुटि की सूचना दें
रिक्ति
1
वेतन
₹37,000 - ₹37,000
नौकरी का प्रकार
संविदा
पूर्णकालिक
आवेदन की अंतिम तिथि
14 सित. 2026
इस नौकरी के बारे में
Apply for the JRF ECE vacancy in NITT. First-class B.E./B.Tech and M.E./M.Tech/M.S. eligible. Salary: Rs 37,000. Last date: 14 Sep 2026.
NITT JRF ECE Recruitment 2026: Overview
National Institute of Technology Tiruchirappalli (NITT) is appointing a Junior Research Fellow in Electronics and Communication Engineering for a processor-design project supported by the Centre for System On-Chip Design and Fabrication. The work centres on an indigenous RISC-V based lightweight edge-AI processor intended for IoT-enabled healthcare applications. This is a hands-on chip-development assignment rather than a general academic fellowship, so the selected researcher will work across architecture, implementation, fabrication support and testing.
The project connects digital VLSI design with embedded computing, edge AI and biomedical applications. You will be expected to turn research ideas into synthesizable hardware, test designs through simulation and prototyping, and help move the processor through the RTL-to-GDSII flow. The assignment also brings hardware and software together: processor programming, C/C++ or Python work, FPGA validation and hardware debugging may all feed into the same research milestones.
Because the processor is intended for resource-constrained healthcare devices, design decisions must balance computing performance with power, area and implementation limits. The fellow can expect an end-to-end view of the development cycle, from lightweight neural-network ideas and quantisation through verification, fabrication coordination, sensor-facing experiments and evaluation of the finished design.
The research team sits in the Department of Electronics and Communication Engineering at the Tiruchirappalli campus under the principal investigator and co-principal investigator named in the notice. The role suits someone who wants exposure to both the design and experimental sides of semiconductor research. Technical writing is part of the work, including project reports and articles that record the design choices, test results and research outcomes.
Service Conditions and Caveats
- Project tenure: The engagement is tied to the research project for 36 months, with continuation reviewed after each 12-month period.
- Higher studies: The selected fellow may register for the NITT PhD or MS-PhD programme, subject to the institute's rules and admission requirements.
- Interview expenses: NITT will not pay TA or DA for attending the interview.
- Original records: Shortlisted candidates must bring their original certificates for checking at the interview.
Application Submission Notes
Send the prescribed application form and scanned supporting documents to jrfmicainitt@gmail.com. Use the exact email subject "JRF Application-CSoCDF PROJECT" so the research team can identify your application. The notice asks for the institute's prescribed format, not a free-form CV alone, and the supporting education and experience records should be self-attested.
जिम्मेदारियाँ
- Develop RTL modules for the lightweight RISC-V edge-AI processor
- Run synthesis, timing analysis, physical-design, and RTL-to-GDSII tasks
- Prototype and verify processor functions on suitable FPGA platforms
- Write C/C++ and Python code for processor testing and hardware-software integration
- Support chip fabrication, post-fabrication testing, and hardware debugging
- Collect and analyse experimental data for healthcare and IoT use cases
- Prepare technical reports, research articles, and project documentation
पात्रता मानदंड
न्यूनतम योग्यता
First-class B.E./B.Tech in Electronics and Communication Engineering plus M.E./M.Tech/M.S. in VLSI Design, Embedded Systems, Microprocessors, or another VLSI-related ECE specialisation
वांछित योग्यता
Knowledge and experience in ASIC design, chip-fabrication flow, and VLSI tools
आवश्यक कौशल
Verilog/SystemVerilog RTL coding; digital VLSI and ASIC design flow; synthesis, static timing analysis, physical design and RTL-to-GDSII; C/C++ and Python; RISC-V architecture; processor programming; hardware-software co-design; AI/ML, quantisation and...
आयु सीमा
18 - 34 वर्ष (14 सित. 2026 तक)
आयु में छूट:
- OBC: 3 वर्ष
- SC/ST: 5 वर्ष
क्या मैं पात्र हूँ?
इस नौकरी की आयु एवं योग्यता के आधार पर त्वरित स्व-जाँच। यह केवल संकेतात्मक है — पुष्टि हमेशा आधिकारिक अधिसूचना से करें।
✓ आप पात्र प्रतीत होते हैं ⚠ सीमारेखा पर — आयु में छूट देखें ✗ आप पात्र नहीं हो सकते
- आप न्यूनतम आयु () से कम हैं।
- आप अधिकतम आयु () से अधिक हैं।
- सामान्य आयु सीमा () से अधिक, लेकिन आरक्षित वर्ग की छूट ( तक) के अंतर्गत आप पात्र हो सकते हैं।
- इस पद के लिए चयनित योग्यता से अधिक योग्यता आवश्यक है।
- योग्यता की स्वतः जाँच नहीं हो सकी — ऊपर दिए गए मानदंड देखें।
तमिलनाडु में केंद्र सरकार नौकरियाँ पाएँ
एक टैप। मेल खाती अधिसूचना प्रकाशित होते ही सूचना पाएँ।
✓ आपको ये अलर्ट मिलेंगे।
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वेतन एवं भत्ते
वेतनमान
Rs. 37,000 per month
चयन प्रक्रिया
- 1 साक्षात्कार
- 2 दस्तावेज़ सत्यापन
अतिरिक्त आवश्यकताएँ
कंप्यूटर ज्ञान आवश्यक
आवेदन कैसे करें
आवेदन का माध्यम: ऑनलाइन
आधिकारिक आवेदन पोर्टल पर जाने के लिए "अभी आवेदन करें" बटन पर क्लिक करें।
आवश्यक दस्तावेज़:
- Prescribed application form
- Self-attested educational certificates and mark sheets
- Self-attested experience certificates, if applicable
- Original certificates for interview verification
अक्सर पूछे जाने वाले प्रश्न
The last date is 14 September 2026 at 5:00 PM. Email the prescribed form and supporting documents before the deadline.
You need a first-class B.E./B.Tech in Electronics and Communication Engineering plus an M.E./M.Tech/M.S. in a VLSI-related ECE specialisation.
Email the prescribed application and self-attested records to jrfmicainitt@gmail.com with the subject "JRF Application-CSoCDF PROJECT".
The fellowship pays Rs. 37,000 per month for the project engagement.
Shortlisted candidates will attend an interview followed by original-document verification. The interview date will be shared by email.
महत्वपूर्ण तिथियाँ
अधिसूचना
24 अग. 2026
आवेदन प्रारंभ
24 अग. 2026
आवेदन की अंतिम तिथि
14 सित. 2026
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