IIT Kharagpur CSE SRF Recruitment 2026

IIT Kharagpur CSE SRF Recruitment 2026: Overview

Indian Institute of Technology Kharagpur (IIT Kharagpur) is recruiting a Senior Research Fellow for a Computer Science and Engineering project led by Rajat Subhra Chakraborty. The project is developing a secure and intelligent indigenous network packet processor on an FPGA, supported by a hardware-based stateful firewall for real-time intrusion detection and prevention. This is a temporary fellowship attached to the project, not a regular institute post.

The work connects digital hardware with network defence. Packet processing has strict performance demands, while a stateful firewall must track traffic behaviour and make security decisions with context. The project therefore needs research that treats hardware architecture, security logic and real-time performance as parts of the same system rather than separate topics.

The desired profile is particularly focused on VLSI implementation. IIT Kharagpur highlights FPGA or ASIC design using Verilog or VHDL, which indicates that the fellow should be comfortable turning an architecture into synthesizable hardware, checking it through simulation and studying how it behaves on a target platform. This suits a researcher who enjoys building and testing digital systems, not only describing them theoretically.

Your contribution should support a dependable prototype. That can involve understanding the packet-processing path, developing hardware modules, creating test cases, checking functional behaviour and comparing resource or timing trade-offs. Because the platform also includes intelligent intrusion detection and prevention, you should be ready to coordinate with researchers handling security algorithms or machine-learning components. Clear interface definitions and careful experiment records will matter when different parts of the system are integrated.

The fellowship offers a specialised research setting for candidates who want to work at the meeting point of FPGA design, computer architecture and cybersecurity. The official project title emphasises an indigenous processor and real-time operation, so practical design choices and reproducibility are central to the work. A strong application should make your prior hardware-design experience easy to identify and connect it directly with the tools named by the institute.

Service Conditions and Caveats

• Nature of engagement: The institute lists the fellowship as a temporary project position. Continuation and work remain connected to the sponsored research assignment.
• Technical focus: The preferred background is hands-on VLSI design on FPGA or ASIC platforms using Verilog or VHDL.
• Project leadership: The coordinator and principal investigator is Rajat Subhra Chakraborty in Computer Science and Engineering.
• System context: Hardware work must fit the wider packet-processor, stateful-firewall and intrusion-detection architecture described by the project.

Application Submission Notes

Use the IIT Kharagpur SRIC recruitment portal and select reference IIT/SRIC/R/NGS/2026/109. The specific project page is the official notice for this fellowship and should be used instead of the general page that lists many SRIC assignments.

• Design digital hardware modules for the network packet processor
• Develop FPGA or ASIC logic using Verilog or VHDL
• Simulate and verify stateful-firewall and packet-processing functions
• Build test cases for real-time intrusion-detection components
• Measure timing, resource use and functional behaviour of prototypes
• Coordinate hardware interfaces with security and intelligent-system modules
• Document designs, experiments and integration findings